Pinout Description

The ATWINC15x0B pins with default peripheral mapping are described in the following table.

Table 1. ATWINC15x0B Pin Description
Pin Number Pin Name Pin Type Description
1 TP_P Analog Test pin/no connect
2 VDD_RF_RX Power Tuner RF supply(1)
3 VDD_AMS Power Tuner BB supply(1)
4 VDD_RF_TX Power Tuner RF supply(1)
5 VDD_BATT_PPA Power PA 1st stage supply(1)
6 VDD_VBATT_PA Power PA 2nd stage supply(1)
7 RFIOP Analog Positive RF differential I/O
8 RFION Analog Negative RF differential I/O
9 SPI_CFG Digital Input Tie to VDDIO through a 1 MΩ resistor to enable the SPI interface
10 GPIO0 Digital I/O, Programmable Pull-Up GPIO0(2)
11 GPIO2/IRQN Digital I/O, Programmable Pull-Up GPIO2(2)/ATWINC15x0B interrupt output; connect to host interrupt input pin
12 UART_TXD Digital I/O, Programmable Pull-Up

UART transmit output from ATWINC15x0B; added for debug and testing only

13 SPI_RXD Digital I/O, Programmable Pull-Up SPI MOSI (Master Out, Slave In) pin
14 VDDC Power Digital core power supply(1)
15 VDDIO Power Digital I/O power supply(1)
16 SPI_SSN Digital I/O, Programmable Pull-Up SPI slave select (active-low)
17 SPI_TXD Digital I/O, Programmable Pull-Up SPI MISO (Master In, Slave Out) pin
18 SPI_SCK Digital I/O, Programmable Pull-Up SPI clock
19 UART_RXD Digital I/O, Programmable Pull-Up

UART receive input to ATWINC15x0B; added for debug and testing only

20 VBATT_BUCK Power Battery supply for DC/DC converter(1)
21 VSW Power Switching output of DC/DC converter(1)
22 VREG_BUCK Power
  • Core power from DC/DC converter(1)
  • Decouple with 10 µF and 0.01 µF capacitor to GND and place these capacitors as recommended in Power Management Unit
23 CHIP_EN Analog
  • Module enable pin
  • High level enables the module and low level places module in Power-Down mode
  • By default, connect a host output to low at power-up; if the host output is tristated, add a 1 MΩ pull-down resistor to ensure a low level at power-up
24 GPIO1/RTC_CLK Digital I/O, Programmable Pull-Up GPIO1/32 kHz clock input(2)
25 TEST_MODE Digital Input Test mode – User must tie this pin to GND
26 VDDIO Power Digital I/O power supply(1)
27 VDDC Power Digital core power supply(1)
28 GPIO3 Digital I/O, Programmable Pull-Up GPIO3(2)
29 GPIO4 Digital I/O, Programmable Pull-Up GPIO4(2)
30 GPIO5 Digital I/O, Programmable Pull-Up GPIO5(2)
31 GPIO6 Digital I/O, Programmable Pull-Up GPIO6(2)
32 I2C_SCL Digital I/O, Programmable Pull-Up
  • I2C slave clock (high-drive pad, see ATWINC15x0B Electrical Characteristics table)

  • Currently, used only for debug development

  • Leave unconnected

  • It is recommended to add Test Point (TP) to this pin

33 I2C_SDA Digital I/O, Programmable Pull-Up
  • I2C slave data (high-drive pad, see ATWINC15x0B Electrical Characteristics table)
  • Currently, used only for debug development

  • Leave unconnected

  • It is recommended to add Test Point (TP) to this pin

34 RESETN Digital Input
  • Active-low hard Reset

  • Assert low to put the module in Reset state

  • Assert high to put the module in Normal state and move it out of Reset state

  • By default, connect a host output to low at power-up; if the host output is tri-stated, add a 1 MΩ pull-down resistor to ensure a low level at power-up

35 XO_N Analog Crystal oscillator N
36 XO_P Analog Crystal oscillator P
37 VDD_SXDIG Power SX power supply(1)
38 VDD_VCO Power VCO power supply(1)
39 VDDIO_A Power Tuner VDDIO power supply(1)
40 TP_N Analog Test pin/no connect
41 PADDLE VSS Power Connect to system board ground
Notes:
  1. 1.For more information, refer to Power Architecture.
  2. 2.Usage of the GPIO functionality is not supported by the ATWINC15x0 firmware. The data sheet will be updated once the support for this feature is added.