Digital I/O Pin Behavior During Power-Up Sequences

The following table represents digital I/O pin states corresponding to the device power modes.

Table 1. ATWINC15x0B Digital I/O Pin Behavior in Different Device States
Device State VDDIO CHIP_EN RESETN Output Driver Input driver Pull-Up/Down Resistor (1)

Power_Down:

core supply off

 High Low Low Disabled (Hi-Z) Disabled Disabled

Power-On Reset:

core supply on, hard reset on

 High High Low Disabled (Hi-Z) Disabled Enabled

Power-On Default:

core supply on, device out of reset but not programmed yet

 High High High Disabled (Hi-Z) Enabled Enabled

On_Doze/

On_Transmit/

On_Receive:

core supply on, device programmed by firmware

 High High High

Programmed by firmware for each pin:

Enabled or Disabled

 Opposite of Output Driver state

Programmed by firmware for each pin:

Enabled or Disabled
Note:
  1. 1. The pull-up/pull-down resistor value used is 96 kΩ ±10%.
Parent topic: Power Management