Power Architecture

The ATWINC15x0B uses an innovative power architecture to eliminate the need for external regulators and reduce the number of off-chip components. This architecture is shown in the following figure. The Power Management Unit (PMU) has a DC/DC Converter that converts VBATT to the core supply used by the digital and RF/AMS blocks. The following table shows the typical values for the digital and RF/AMS core voltages. The PA and eFuse are supplied by dedicated LDOs, and the VCO is supplied by a separate LDO structure.

Figure 1. ATWINC15x0B Power Architecture

Table 1. ATWINC15x0B Power Consumption
Parameter	Typical
RF/AMS Core Voltage (VREG_BUCK)	1.25V
Digital Core Voltage (VDDC)	1.10V

The power connections in Figure 1 provide a conceptual framework for understanding the ATWINC15x0B power architecture. For more details on reference design, see Reference Design for an example of power supply connections, including proper isolation of the supplies used by the digital and RF/AMS blocks.