Automatic Sampling Delay Variation (ASDV) together with sample accumulation can be helpful in suppressing harmonic noise with unknown base frequency. If ADSV is enabled, the ADC will cycle through the supported sampling delay configurations, increasing the delay by one ADC clock (CLK_ADC) cycle for every conversion. The varying sampling delay can provide noise attenuation over a broader frequency range compared to a fixed sampling delay, but does so at the cost of a reduced attenuation factor. In situations where the harmonic noise frequency is known or measurable, it is recommended to use a sampling delay tuned to suppress the present frequency components. ADSV can be enabled by writing the ADSV bit to the Control D (ADC.CTRLD) register.