MIV_RV32 is a processor core designed to implement the RISC-V instruction set. The core can be configured to have AHB, APB3, and AXI3/4 bus interfaces for peripheral and memory accesses. Figure 1 shows the top-level block diagram of the Mi-V subsystem built on RT PolarFire FPGA.
The user application to be executed on Mi-V processor can be stored in μPROM, sNVM, or an external SPI Flash. At device power-up, the system controller initializes the designated TCM with the user application. The system Reset is released after the TCM initialization is completed. If the user application is stored in SPI Flash, the System Controller uses the SC_SPI interface for reading the user application from SPI Flash. The given user application performs DDR3 memory access and prints the messages to a UART terminal, and blinks user LEDs on the board.
