The following table lists the IP blocks used in the Mi-V processor subsystem reference design and their function.
| IP Name | Function |
|---|---|
| INIT_MONITOR | The PolarFire® Initialization Monitor gets the status of device and memory initialization. |
| reset_syn | This is the CORERESET_PF IP instantiation which generates a system-level synchronous Reset for the Mi-V subsystem. |
| CCC_0 | The PolarFire® Clock Conditioning Circuitry (CCC) block takes an input clock of 50 MHz from the on-board oscillator and generates a 53.3 MHz fabric clock for the Mi-V processor subsystem and other peripherals. |
| MIV_RV32_C0 (Mi-V Soft Processor IP) | The Mi-V soft processor default Reset Vector Address value is 0x8000_0000. After the device reset, the processor executes the application from 0x8000_0000. TCM is the main memory of the Mi-V processor and is memory mapped to 0x8000_0000. The TCM gets initialized with the user application which stored in the SPI Flash. In the Mi-V processor memory map, the 0x8000_0000 to 8000_FFFF range is defined for TCM memory interface and the 0x6000_0000 to 0x6FFF_FFFF range is defined for the APB interface. The 0x8001_0000 to 8FFF_FFFF range is defined for the AXI interface which is used to interface the external DDR memory. |
| reset_syn_1 | This is the CORERESET_PF IP instantiation which generates a system-level synchronous Reset for DDR3_0. |
| DDR3_0 (DDR3 Controller IP) | This IP is used to perform DDR3 read and write operations. The data-width is set to 32-bit and memory clock frequency is set to 533 MHz, which is generated from a reference clock frequency input 53.3 MHz using a clock multiplier (x10) internal to the DDR3 IP. The DDR3 PLL generates a 533 MHz DDR3 memory clock frequency and a 133.25 MHz DDR3 AXI clock frequency. |
| COREAXI4INTERCONNECT_C1 | AXI4 interconnect used to interface the Mi-V soft processor with the DDR3 Controller IP. |
| COREGPIO_0 | The CoreGPIO IP controls the on-board LEDs using GPIOs. It is connected to Mi-V soft processor as an APB slave. |
|
UART_apb |
The UART_apb IP controls the UART peripherals used for serial communication. |
| COREJTAGDebug | Used to debug the Mi-V soft processor. |
| APB3 | APB3 bus interconnect to interface with peripherals. |