By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short glitches when the inputs change value. These glitches can be removed by clocking through filters, if demanded by application needs. The Filter Selection bits in LUT Control register (LUTCTRLx.FILTSEL) define the synchronizer or digital filter options. When a filter is enabled, the output will be delayed by three to four GCLK_CCL cycles. One APB clock cycle after a LUT is disabled, all corresponding internal filter logic is cleared.
The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a falling edge, the truth table should be programmed to provide the opposite levels. The edge detector is enabled by writing a one to the Edge Selection bit in LUT Control register (LUTCTRLx.EDGESEL). In order to avoid unpredictable behavior, a valid filter option must be enabled as well. Refer to the Filter Selection bit group in the LUT Control x register (LUTCTRLx.FILTSEL) for valid filter selections.