The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. These modes are illustrated in the following table and figure.
| Mode | CPOL | CPHA |
|---|---|---|
| 0 | 0 | 0 |
| 1 | 0 | 1 |
| 2 | 1 | 0 |
| 3 | 1 | 1 |
Note: The ATWINC3400-MR210xA firmware uses
SPI MODE 0to communicate with the host.
The red lines in the following figure correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.
Figure 1. SPI Slave Clock Polarity and Clock Phase Timing
The SPI timing is provided in the following figure and table.
Figure 2. SPI Timing Diagram (SPI Mode CPOL = 0, CPHA = 0)
| Parameter | Symbol | Min. | Max. | Units |
|---|---|---|---|---|
| Clock Input Frequency(2) | fSCK | — | 48 | MHz |
| Clock Low Pulse Width | tWL | 4 | — | ns |
| Clock High Pulse Width | tWH | 5 | — | |
| Clock Rise Time | tLH | 0 | 7 | |
| Clock Fall Time | tHL | 0 | 7 | |
| TXD Output Delay(3) | tODLY | 4 | 9 from SCK fall | |
| RXD Input Setup Time | tISU | 1 | — | |
| RXD Input Hold Time | tIHD | 5 | — | |
| SSN Input Setup Time | tSUSSN | 3 | — | |
| SSN Input Hold Time | tHDSSN | 5.5 | — |
Notes:
- 1.The timing is applicable to all SPI modes.
- 2.The maximum clock frequency specified is limited by the SPI Slave interface internal design; the actual maximum clock frequency can be lower and depends on the specific PCB layout.
- 3.The timing is based on 15 pF output loading. Under all conditions, tLH + tWH + tHL + tWL must be less than or equal to 1/ fSCK.