The CCL peripheral has one pair of Look-up Tables (LUTs) on tinyAVR 0- and 1-series, two pairs of LUTs on megaAVR 0-series, and three pairs of LUTs on AVR DA devices. Each LUT consists of three inputs with a truth table, a synchronizer, a filter, and an edge detector. Each LUT can generate an output as a user-programmable logic expression with three inputs; any device with CCL will have a minimum of two LUTs available. These inputs can be individually masked. The output can be generated from the combinatorial inputs and be filtered to remove spikes. An optional sequential logic module can be enabled. The inputs to the sequential module are individually controlled by two independent, adjacent LUT outputs (LUT0/LUT1), enabling complex waveform generation.
It is possible to create simple logic blocks (AND, OR, NAND, NOR, XOR) or custom ones using the truth table up to three inputs on each of the LUTs. When more than three inputs are required, multiple connected LUTs are used to create logic gates.
To define a combinational specific logic function, the CCL module uses truth tables. A truth table shows how the logic circuit responds to various combinations of three inputs. Each combination of the Input (IN[2:0]) bits corresponds to one bit in the respective TRUTHn register. Below are some examples of how to create some common logic gates using three inputs.
0x80
to be used in the TRUTHn
register.CCL.TRUTHn = 0x80;
0x96
to be used in the TRUTHn
register.CCL.TRUTHn = 0x96;
When any of the three inputs are not needed, the unused input will be masked (tied
low). Only the TRUTH bits where the masked input is ‘0
’ can be used
when looking at the truth table to determine how the bits need to be set to get the
wanted logic. Below are some examples of where various inputs are masked.
Some applications require more than three logic inputs. The CCL module provides the option to link internally the next LUTs direct output to a LUT input. For example, if LUT0 and LUT1 are used to create a logic function, the LUT1 output can be connected to the LUT0 input internally.
Using the CCL eliminates the need for external logic, reduces Bill of Materials (BOM) cost, and enables the CPU to handle time-critical parts of the application more efficiently.