The initialization delay for the PGA does not start when the LOWLAT bit is ‘0
’. This may cause a corrupt conversion when the PGA is the module with the slowest initialization time. When using the internal references, this is not an issue because of a slower initialization delay.
Set the ADC in low latency mode by setting the Low Latency (LOWLAT) bit in the Control A (CTRLA) register to ‘1
’.
Rev. A |
X |