Important Points to be Noted when using External Interrupts

  1. 1.If a level triggered interrupt is used for waking up the device from Power-down, the required level must be held long enough for the MCU to complete the wake-up, to trigger the level interrupt. If the level disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated.
  2. 2.Both INT7:0 and pin change interrupts can be used to wake up the device from any sleep modes. But INT7:4 should be configured to sense level interrupt to wake up the device from sleep mode other than idle mode.
  3. 3.If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.
  4. 4.When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register.
  5. 5.Before enabling an interrupt, it is recommended to clear the flag bit of the corresponding interrupt because when the flag bit is set, the interrupt will be triggered the moment we enable the interrupt.
  6. 6.If enabled, interrupts will be triggered even when the pins are configured as outputs. This provides a way of generating a software interrupt.
  7. 7.If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the power-down, power-save, and standby sleep modes.
  8. 8.Once the CPU enters the ISR, the global interrupt enable bit (I-bit) in SREG will be cleared so that all other interrupts are disabled. In order to use nested interrupts, the I-bit has to be set by software when the CPU enters an ISR.