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tinyAVR® 2 Family ATtiny3224/3226/3227
Introduction
tinyAVR® 2 Family Overview
1 Memory Overview
2 Peripheral Overview
Features
1 Block Diagram
2 Pinout
2.1 14-Pin SOIC, TSSOP
2.2 20-Pin SOIC, SSOP
2.3 20-Pin VQFN
2.4 24-Pin VQFN
3 I/O Multiplexing and Considerations
3.1 I/O Multiplexing
4 Hardware Guidelines
4.1 General Guidelines
4.2 Connection for Power Supply
4.3 Connection for RESET
4.4 Connection for UPDI Programming
4.5 Connecting External Crystal Oscillators
4.6 Connection for External Voltage Reference
5 Conventions
5.1 Numerical Notation
5.2 Memory Size and Type
5.3 Frequency and Time
5.4 Registers and Bits
5.5 ADC Parameter Definitions
6 AVR® CPU
6.1 Features
6.2 Overview
6.3 Architecture
6.4 Arithmetic Logic Unit (ALU)
6.5 Functional Description
6.6 Register Summary
6.7 Register Description
7 Memories
7.1 Overview
7.2 Memory Map
7.3 In-System Reprogrammable Flash Program Memory
7.4 SRAM Data Memory
7.5 EEPROM Data Memory
7.6 USERROW - User Row
7.7 LOCKBIT - Memory Sections Access Protection
7.8 FUSE - Configuration and User Fuses
7.9 SIGROW - Signature Row
7.10 I/O Memory
8 Peripherals and Architecture
8.1 Peripheral Address Map
8.2 Interrupt Vector Mapping
8.3 SYSCFG - System Configuration
9 General Purpose I/O Registers
9.1 Register Summary
9.2 Register Description
10 NVMCTRL - Nonvolatile Memory Controller
10.1 Features
10.2 Overview
10.3 Functional Description
10.4 Register Summary
10.5 Register Description
11 CLKCTRL - Clock Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary
11.5 Register Description
12 SLPCTRL - Sleep Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
13 RSTCTRL - Reset Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary
13.5 Register Description
14 CPUINT - CPU Interrupt Controller
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary
14.5 Register Description
15 EVSYS - Event System
15.1 Features
15.2 Overview
15.3 Functional Description
15.4 Register Summary
15.5 Register Description
16 PORTMUX - Port Multiplexer
16.1 Overview
16.2 Register Summary
16.3 Register Description
17 PORT - I/O Pin Configuration
17.1 Features
17.2 Overview
17.3 Functional Description
17.4 Register Summary - PORTx
17.5 Register Description - PORTx
17.6 Register Summary - VPORTx
17.7 Register Description - VPORTx
18 BOD - Brown-out Detector
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary
18.5 Register Description
19 VREF - Voltage Reference
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary
19.5 Register Description
20 WDT - Watchdog Timer
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary
20.5 Register Description
21 TCA - 16-bit Timer/Counter Type A
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary - Normal Mode
21.5 Register Description - Normal Mode
21.6 Register Summary - Split Mode
21.7 Register Description - Split Mode
22 TCB - 16-Bit Timer/Counter Type B
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary
22.5 Register Description
23 RTC - Real-Time Counter
23.1 Features
23.2 Overview
23.3 Clocks
23.4 RTC Functional Description
23.5 PIT Functional Description
23.6 Crystal Error Correction
23.7 Events
23.8 Interrupts
23.9 Sleep Mode Operation
23.10 Synchronization
23.11 Debug Operation
23.12 Register Summary
23.13 Register Description
24 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
24.1 Features
24.2 Overview
24.3 Functional Description
24.4 Register Summary
24.5 Register Description
25 SPI - Serial Peripheral Interface
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary
25.5 Register Description
26 TWI - Two-Wire Interface
26.1 Features
26.2 Overview
26.3 Functional Description
26.4 Register Summary
26.5 Register Description
27 CRCSCAN - Cyclic Redundancy Check Memory Scan
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary
27.5 Register Description
28 CCL - Configurable Custom Logic
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 AC - Analog Comparator
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary
29.5 Register Description
30 ADC - Analog-to-Digital Converter
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary
30.5 Register Description
31 UPDI - Unified Program and Debug Interface
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary
31.5 Register Description
32 Instruction Set Summary
33 Electrical Characteristics
33.1 Disclaimer
33.2 Absolute Maximum Ratings
33.3 General Operating Ratings
33.4 Power Considerations
33.5 Power Consumption
33.6 Wake-Up Time
33.7 Peripherals Power Consumption
33.8 BOD and POR Characteristics
33.9 External Reset Characteristics
33.10 Oscillators and Clocks
33.11 I/O Pin Characteristics
33.12 USART
33.13 SPI
33.14 TWI
33.15 VREF
33.16 ADC
33.17 TEMPSENSE
33.18 AC
33.19 UPDI
33.20 Programming Time
34 Typical Characteristics
34.1 Power Consumption
34.2 GPIO
34.3 VREF Characteristics
34.4 BOD Characteristics
34.5 ADC Characteristics
34.6 TEMPSENSE Characteristics
34.7 AC Characteristics
34.8 OSC20M Characteristics
34.9 OSCULP32K Characteristics
35 Ordering Information
36 Package Drawings
36.1 Online Package Drawings
36.2 Package Marking Information
36.3 14-Pin SOIC
36.4 14-Pin TSSOP
36.5 20-Pin SOIC
36.6 20-Pin SSOP
36.7 20-Pin VQFN
36.8 20-Pin VQFN Wettable Flanks
36.9 24-Pin VQFN
36.10 24-Pin VQFN Wettable Flanks
37 Data Sheet Revision History
37.1 Rev.B - 12/2021
37.2 Rev.A - 09/2021
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