The sinusoidal data is divided into six arrays for the DMA controller to
easily point its address as the source, as shown in
Figure 4-1. The three windings require the same
signal, phase-shifted by 120°, therefore a single set of sinusoidal data can be used.
Figure 1. Sinusoidal Data Look-Up
Table
Each array consists of 32 16-bit elements. These arrays are stored in the
Program Flash Memory (PFM) of the MCU. Using the DMA controller, the address of the
first element is set as the DMA source address. The data is transferred from the PFM to
the PWM Duty Cycle register, which is set as the DMA destination address. The DMA
controller requires the size of the destination address to be a multiple of the source
address size and vice versa. The DMAxDSZ register determines the destination size, while
the DMAxSSZ register determines the size of the source. The PWM Duty Cycle register is a
16-bit register, which makes the value of the DMAxDSZ register equal to 2 bytes. The
value of DMAxSSZ depends on the array size stored in the PFM. It can be calculated using
Equation 4-1.
There are two events that access or modify the settings of the DMA
controller; one is during Hall state transition, and the other is during motor angular
position interrupt. When a Hall state change is detected, the DMA controller source
address register is loaded by the firmware, depending on both the sector position and
direction. Changing the addresses during operation requires enabling and disabling the
DMA channel on the run. A lock and unlock sequence is required to do this. On the other
hand, the motor angular position interrupt triggers the DMA controller to increment the
DMA source address, pointing to the next element on the array until all elements have
been loaded to the destination or another Hall state change is detected.
Each DMA channel's destination address is pointed to the PWM slice register
where the variable voltage is set. The switching frequency for motor control
applications depends on the motor's inductance. If the motors current can change at a
fast rate, the switching frequency should be high enough to avoid core saturation. In
this application, the switching frequency was set to 40 kHz, catering the need to
provide high frequency and high resolution for motor operation.
Equation 4-2 shows the calculation of the PWM period, in
reference to the frequency selected. The sinusoidal data that is used in this
application are duty cycle values, based on the PWM resolution and PWM period, which can
be calculated using
Equation 4-3. Center-Aligned mode is selected to produce two
pulses line-to-line in each period. By doing this, the ripple current is reduced while
not increasing the switching loss in power devices. The PWM registers are
double-buffered. It requires an external source or LD bit to be triggered. In this
application, DMA is used as an external load event. Every time the DMA channel
successfully transfers a message, a request to load is made. The buffer updates every
other request.
To drive the three-phase motor with sinusoidal currents, the CWG peripheral
is used. The MOSFET driver of the three-phase BLDC motor consists of three half-bridges,
one for each motor terminal. Each half-bridge consists of two switches, which require
complementary PWM signals. Because of this, the CWG modules are configured in Half
Bridge mode, where each generates two output signals that resemble the true and inverted
versions of the input PWM. The CWGxA input is configured for the high-side switches,
while the CWGxB input is configured for the low-side switches of the driver.
Figure 4-2 shows the CWG output representation for each half bridge.
Figure 5. CWG Output
Since power MOSFETs take a finite amount of time to switch on or off, there
may be a time where both switches of a half bridge turn on. It creates a low resistance
path from the source to the ground that could cause a short circuit. This event is
called shoot-through. In CWG, a dead-band delay is inserted to prevent shoot-through
current during an output level transition. Dead-band delay is a time delay inserted
between the switch transition to prevent conduction of high and low-side switches at the
same time. Dead-band delays can be inserted in the rising or falling edge of the input
source. Dead-band counters are set on CWGxDBR and CWGxDBF registers.