Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A register (WDT.CTRLA) is synchronized when written. The Synchronization Busy flag (SYNCBUSY) in the STATUS register (WDT.STATUS) indicates if there is an ongoing synchronization.
Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.
The WDR
instruction will need two to three cycles of the WDT
clock in order to be synchronized. Issuing a new WDR
instruction while a
WDR
instruction is being synchronized will be ignored.