The Buffer mode is enabled by setting the BUFEN bit in
SPIn.CTRLB. The BUFWR bit in SPIn.CTRLB has no effect in Master mode.
In Buffer mode, the system is double-buffered in the transmit direction
and triple-buffered in the receive direction. This influences the data
handling the following ways:
- 1.New bytes to be
sent can be written to the Data register (SPIn.DATA) as long as
the Data Register Empty Interrupt Flag (DREIF) in the Interrupt
Flag Register (SPIn.INTFLAGS) is set. The first write will be
transmitted right away and the following write will go to the
Transmit Buffer register.
- 2.A received byte
is placed in a two-entry RX FIFO comprised of the First and
Second Receive Buffer registers immediately after the
transmission is completed.
- 3.The Data register
is used to read from the RX FIFO. The RX FIFO must be read at
least every second transfer to avoid any loss of data.
If both the Shift register and the Transmit Buffer register becomes empty, the
Transfer Complete Interrupt Flag (TXCIF) in the Interrupt Flags register (SPIn.INTFLAGS)
will be set. This will cause the corresponding interrupt to be executed if this interrupt
and the global interrupts are enabled. Setting the Transfer Complete Interrupt Enable
(TXCIE) in the Interrupt Control register (SPIn.INTCTRL) enables the Transfer Complete
Interrupt.