Writing this bit to ‘1’ enables interrupt on the Slave Data Interrupt Flag (DIF) in the Slave Status register (TWIn.SSTATUS). A TWI slave data interrupt will be generated only if this bit, the DIF, and the Global Interrupt Flag (I) in CPU.SREG are all ‘1’.

Writing this bit to ‘1’ enables an interrupt on the Slave Address or Stop Interrupt Flag (APIF) in the Slave Status register (TWIn.SSTATUS). A TWI slave Address or Stop interrupt will be generated only if this bit, APIF, and the Global Interrupt Flag (I) in CPU.SREG are all ‘1’.

The slave stop interrupt shares the interrupt flag and vector with the slave address interrupt. The TWIn.SCTRAL.PIEN must be written to ‘1’ in order for the APIF to be set on a stop condition. When the interrupt occurs the TWIn.SSTATUS.AP bit will determine whether an address match or a stop condition caused the interrupt.

Writing this bit to ‘1’ enables APIF to be set when a Stop condition occurs. To use this feature the system frequency must be 4x the SCL frequency.

If this bit is written to ‘1’, the slave address match logic responds to all received addresses.

If this bit is written to ‘0’, the address match logic uses the Slave Address register (TWIn.SADDR) to determine which address to recognize as the slaves own address.

Writing this bit to ‘1’ enables the slave Smart mode. When the Smart mode is enabled, issuing a command with CMD or reading/writing DATA resets the interrupt and operation continues. If the Smart mode is disabled, the slave always waits for a CMD command before continuing.

Writing this bit to ‘1’ enables the TWI slave.