Hierarchical SmartDesigns can be created by pressing CTRL+H shortcut key. Observe the following guidelines when creating a Hierarchical SmartDesign:
- Default name of the "Hierarchical SmartDesign" is: hier_[index].
- Top-level ports are created in the Hierarchical SmartDesign for all the unconnected instance pins.
- Port names for the Hierarchical SmartDesign is created using this formula: [instance_name] + "_pin_" + [pin_name].
- PAD ports do not follow the same naming rules and are promoted to top level automatically.
- If port name already exists, index suffixing is added to the name.
- Sliced ports are created like the regular bus ports.
- A Hierarchical SmartDesign can be created out of a single instance.
- Creating Hierarchical SmartDesign out of the ports is not allowed. At least one instance needs to be selected.
The following figures show an example of a Hierarchical SmartDesign consisting of 3 AND gates.
Figure 1. Hierarchical SmartDesign (Port Names Folded Inside the Block)
Figure 2. Hierarchical SmartDesign (Port Names Expanded Inplace Inside the Block Showing the AND Gates)
