| BIF |
Abbreviation for bus interface. Logical grouping of ports or pins that represent a single functional purpose. May contain both input and output, scalars, or buses. A bus interface is a specific mapping of a bus definition onto a component instance. |
| Bus |
An array of scalar ports or pins, where all scalars have a common base name and have unique indexes in the bus. |
| Bus Definition |
Defines the signals that comprise a bus interface. Includes which signals are present on an initiator, target, or system interface, signal direction, width, default value, etc. A bus definition is not specific to a logic or design component but is a type or protocol. |
| Bus Interface Net |
A connection between two or more compatible bus interfaces Canvas A visual representation of the canvas for placing components and stitching the components to create a working design. |
| Driver |
A driver is the origin of a signal on a net. The input and target BIF ports of the top-level or the output and Initiator BIF ports from instances are drivers. |
| Instance |
A block-like item with pins on either side of it. These are connected together to create designs. You may have multiple instances of a single component in your design. For each specific instance, you usually will have custom connections that differ from other instances of the same component. |
| Net |
A wire that connects pins/ports in a design PAD The property of a port that must be connected to a design’s top- level port. PAD ports will eventually be assigned to a package pin. In SmartDesign, these ports are automatically promoted to the top-level and cannot be modified. |
| Pins |
Pins are the inputs/outputs/inouts of an instance that a net can be attached to for connection with other components in the design. By default, pins are placed on either the left (inputs) or the right side (outputs and inouts) of the instance. Pin order can be modified for a cleaner, less cluttered connection. |
| Port |
A port is like a pin, but it is not attached to an instance. It acts as a way of letting a net connect to the outside world. A port has a direction (input, output, bidirectional) and may be referred to as a ‘scalar port’ to indicate that only a single unit-level signal is involved. In contrast, a bus interface on an instance may be considered as a non-scalar, composite port. |
| Macro |
A type of very basic instance that typically has a special well- known shape associated with it. Inside of more complicated instances will be connected macros to do a more complicated function. Macros are specific to the technology family. Macros are listed in the Basic Macro group in the Catalog. |
| HDL File |
A specially formatted text-file that describes the designs you create in a standard way. |
| Viewport |
The rectangular view area of the canvas that is visible to you. You can move the viewport around on the canvas or zoom in/out to view your design. Showing the whole canvas would be too large in most cases. |
| Initiator BIF |
Initiator Bus Interface. The bus interface that initiates a transaction (such as a read or write request) on a bus. |
| Target BIF |
Target Bus Interface. The bus interface that responds to a transaction (such as a read or write request) on a bus. |
| System Bus Interface |
Interface that is neither initiator nor target; enables specialized connections to a bus. |
| Slice |
A slice is created from a bus. It is a portion of the bus and it contains some but not all scalar members of the bus. |
| Top-Level Port |
An external interface connection to the outside world. Scalar if a 1-bit port, bus if a multiple-bit port or a Bus Interface (BIF). These are connected to the pad/package pins of the FPGA device. |
| Pin Group |
A grouping of pins (scalar or bus) you create for easy connection or identification. |