SmartDesign in the Libero SoC Design Flow

SmartDesign allows create a component in which you can stitch together HDL modules, HDL Cores, configures IPs, re-usable design blocks, Microchip primitives and lower level SmartDesign components, and other components types. A SmartDesign can be the top level of your design or a sub-module of your design. The Files tab lists your SmartDesign files in alphabetical order.

1. 1.Instantiating components: This step is analogous to inserting design components onto the canvas. In this step you add one or more building blocks, HDL modules, components, and schematic modules from the Project Manager to your design. The components can be design blocks, IP cores from the Catalog, basic macros, design blocks, and other SmartDesign components files available in the Project Manager Design Hierarchy tab Component node or the Component tab into the Libero SoC project.
2. 2.Connecting bus interfaces: In this step, you can add connectivity via standard bus interfaces to your design. This step is optional and can be skipped if you prefer manual connections. Components generated from the Catalog may include predefined interfaces that allow for automatic connectivity and design rule checking when used in a design.
3. 3.Connecting instances: The Canvas allows create manual connections between ports of the instances in your design. Unused ports can be tied off to GND or VCC; input buses can be tied to a constant, and you can leave an output open by marking it as unused.
4. 4.Generating the SmartDesign component: In this step, you generate the SmartDesign component HDL file. This component can be used by downstream processes, such as synthesis and simulation, or you can instantiate this SmartDesign component into another SmartDesign. When you generate your SmartDesign, the tool invokes the Design Rules Checker to verify the connectivity of your design. Undriven and floating ports, along with other Design Rule Check (DRC) violations, are reported in the Log/Message window. Any errors must be addressed before a component can be generated successfully. The design flow cannot proceed if a component used in the design is not generated.