Instantiating into your SmartDesign

  1. 1.Instantiating Into Your SmartDesign
  2. 2.How do I create my first SmartDesign?
  3. 3.I have a block that I wrote in VHDL (or Verilog), can I use that in my SmartDesign?
  4. 4. My HDL module has Verilog parameters or VHDL generics declared, how can I configure those inSmartDesign?
Parent topic: Appendix A - FAQ