Introduction

SmartDesign is a visual block-based design creation and entry tool for the instantiation, configuration, and connection of Microchip IPs, user-generated IPs, and custom and glue-logic HDL modules. This tool provides a canvas for stitching together the various design components. The final result from SmartDesign is a design-rule-checked and synthesis-ready HDL file. A generated SmartDesign can be the entire FPGA design or a component subsystem to be reused in a larger design.

The following design objects can be instantiated in the SmartDesign Canvas:

• Microchip IP Cores
• User-generated or third-party IP Cores
• HDL design files
• HDL Core design files
• Basic macros
• Other SmartDesign components generated from SmartDesign in the current Libero^® SoC project or imported from other Libero SoC projects
• Reusable design blocks published from Libero SoC