The following are the more common DRC errors and the corrective actions you need to take:
| DRC Error | Description |
|---|---|
| Unused Instance | You must remove this instance or connect at least one output pin to the rest of the design. |
| Out-of-date Instance | You must update the instance to reflect a change in the component referenced by this instance. |
| Undriven Pin | To correct the error, you must connect the pin to a driver or change the state, that is tie low (GND), tie high (VCC), tie to Constant or marked unused. |
| Floating Driver | You can mark the pin unused if it is not going to be used in the current design. Pins marked unused are ignored by the Design Rules Check. |
| Unconnected Bus Interface | You must connect this bus interface to a compatible port because it is a required connection. |
| Required Bus Interface Connection | You must connect this bus interface before you generate the design. These are typically silicon connection rules. |
| Exceeded Allowable Instances for Core | Some IP cores can only be instantiated a certain number of times for legal design. For example, there can only be one Arm® Cortex®-M1 or CoreMP7 in a design due to silicon limitations. You must remove the extra instances. This check is technology-dependent. |
| Incompatible Family Configuration | The instance is not configured to work with this project's Family setting. Either it is not supported by this family or you need to re-instantiate the core. This DRC check is family/technology-dependent. |
| No RTL License, No Obfuscated License, No Evaluation License | You do not have the proper license to generate this core. Contact Microchip SoC to obtain the necessary license. |
| No Top level ports | There are no ports at the top-level. To auto-connect top-level ports, right click the Canvas and choose Auto-connect |
| Self-Instantiation | The component <component_name> corresponds to the current SmartDesign design. A component cannot instantiate itself. Note: This message is reported only in the Log Window.
|
| Bus interface data width mismatch | There is a data width mismatch between MIV_RV32IMA_L1_AXI_C0_0:MMIO_MST_AXI4:MMIO_AXI_0_W_BITS_DATA[0-63] and COREAXI4INTERCONNECT_C0_0:AXI4mmaster1:MASTER1_WDATA[0-31], which may result in loss of data. To correct the error, make initiator (driver) BIF pin write port width less than or equal to target BIF pin write port width as per port name shown in the DRC message. Another way to correct the error is to make target BIF pin read port width less than or equal to initiator (driver) BIF pin read port width as per port name shown in the DRC message. |
| Bus interface ID width mismatch | There is an ID width mismatch between MIV_RV32IMA_L1_AXI_C0_0:MEM_MST_AXI4:MEM_AXI_0_AW_BITS_ID[0-3] and COREAXI4INTERCONNECT_C0_0:AXI4mmaster0:MASTER0_AWID[0-1], which may result in loss of data. To correct the error, make initiator (driver) BIF Pin AWID/WID/ARID port width less than or equal to target BIF pin AWID/WID/ARID port width as per port name shown in the DRC message. Another way to correct the error is to make target BIF pin RID/BID port width less than or equal to initiator (driver) BIF pin RID/BID port width as per port name shown in the DRC message. |