Contents

Introduction 1. About SmartDesign 1.1. Canvas Layout 1.2. SmartDesign in the Libero SoC Design Flow 1.3. Instantiating Components into SmartDesign Canvas 1.4. SmartDesign Canvas and Component Display 1.5. SmartDesign Tcl Commands 2. SmartDesign Actions, Hotkeys, and Menu Items 2.1. SmartDesign Actions 2.2. SmartDesign Hotkeys 2.3. Click and Drag Operations 3. SmartDesign User Actions 3.1. Net Actions 3.1.1. Connect 3.1.2. Go to Driver 3.1.3. Highlight 3.1.4. Rename 3.1.5. Delete 3.2. Instance Actions 3.2.1. Configure 3.2.2. Modify HDL 3.2.3. Highlight 3.2.4. Rename 3.2.5. Delete 3.2.6. Expand Inplace and Fold Instance 3.2.7. Replace Component 3.2.8. Update Component Version 3.2.9. Modify Pin Order 3.2.10. Reset Pin Order 3.2.11. Remove Connections 3.2.12. Help 3.3. Pin/Port Actions 3.3.1. Connect 3.3.2. Disconnect 3.3.3. Promote to Top-Level 3.3.4. Go to Driver 3.3.5. Magnify Pin 3.3.6. Highlight 3.3.7. Modify and Rename 3.3.8. Delete 3.3.9. Expanding and Collapsing Bus 3.3.10. Flip Bit Order 3.3.11. Create Slices 3.3.12. Custom Slices 3.3.13. Edit Slices 3.3.14. Clear Attributes 3.3.15. Mark Unused 3.3.16. Invert 3.3.17. Tie High and Tie Low 3.3.18. Tie Constant 3.3.19. Add Pin to New Group and Add Pin to Group 3.3.20. Rename (Group) 3.3.21. Show and Hide BIF Pins 3.4. Copy, Cut, and Paste 3.4.1. Copy and Paste 3.4.2. Cut and Paste 3.4.3. Copy Name 3.4.4. Best Practices 3.5. View Memory Map 4. Designing with SmartDesign 4.1. Create a Top-Level SmartDesign Component 4.2. Creating Hierarchical Smart Design 4.2.1. Best Practices 4.3. Flattening Hierarchical Smart Design 4.3.1. Best Practices 4.3.2. Special Cases for Flattening Hierarchical Smart Design 4.4. Manage Synthesis Attributes 4.4.1. Managing Synthesis Attributes from Canvas 4.5. Configure/Instantiate Components 4.5.1. Configure 4.5.2. Instantiate 4.5.3. Importance of .cxf Files in SmartDesign 4.6. Make the Connections 4.6.1. Smart Search and Connect 4.6.1.1. Item Tree 4.6.1.2. Search Bar 4.6.1.3. Filter Menu 4.6.1.4. Actions and Toolbar 4.6.1.5. Connection Buttons 4.6.2. Control + Click Connection 4.6.3. Modify Pin Order Before Connections 4.6.4. Splitting the Bus Before Connections 4.6.5. Search Design Objects to Connect 4.6.5.1. Find Window 4.6.5.2. Net Filter in SmartDesign Canvas 4.7. Add or Modify Top-Level Ports 4.7.1. Add Prefixes to Bus Interface and Group Names on Top-level Ports 4.7.2. Adding and Removing Ports 4.7.3. Modify/Rename Port 4.8. Invoke DRC on the Design 4.9. Generate the Top-Level Component 4.9.1. Recursive Generation 4.9.2. Non-Recursive Generation 5. Design Navigation Features 5.1. Expand and Fold Instance 5.1.1. Expand Inplace and Low-Level Blocks 5.1.2. Component Regeneration 5.2. Magnify Pin 5.3. Go To Driver 6. Appendix A - FAQ 6.1. Instantiating into your SmartDesign 6.2. Working in SmartDesign 6.3. Working With Processor-Based Designs in SmartDesign 6.4. VHDL Construct Support in SmartDesign 6.5. Making the Design Look Nice 6.6. Generating the Design 6.7. General Questions 6.7.1. What is SmartDesign? 6.7.2. How do I create my first SmartDesign? 6.7.3. What are the differences between the old and new SmartDesign Canvas? 6.7.4. What must I do with my current SmartDesign component when I switch to the new SmartDesign? 6.8. Instantiating Into Your SmartDesign 6.8.1. Where is the list of cores that I can instantiate into my SmartDesign? 6.8.2. Can I use a block that I wrote in VHDL (or Verilog) in my SmartDesign? 6.8.3. My HDL module has Verilog parameters or VHDL Generics declared, how can I configure those in SmartDesign? 6.9. Working in SmartDesign 6.9.1. How do I make manual connections? 6.9.2. How do I connect a pin to the top level? 6.9.3. I made a connection mistake. How do I disconnect two pins? 6.9.4. How can I apply simple 'glue' logic between cores? 6.9.5. My logic is more complex than inversion and tie offs - what else can I do? 6.9.6. How do I create a new top-level port for my design? 6.9.7. How do I rename one of my instances? 6.9.8. How do I rename my top-level port? 6.9.9. How do I rename my group pins? 6.9.10. I need to reconfigure one of my Cores, can I just double click the instance? 6.9.11. I want more Canvas space to work with! 6.10. Working with Processor-Based/AMBA-Bus Designs 6.10.1. I need my peripheral at a specific address or slot 6.10.2. How do I view the Memory Map of my design? 6.10.3. How can I connect my own HDL block as a peripheral on the AMBA bus? 6.10.4. How do I start writing my application code for my design? 6.10.5. How do I simulate my processor design? 6.11. VHDL Construct Support in SmartDesign 6.11.1. What VHDL constructs are supported? 6.11.2. How can I import files with VHDL Special Types into SmartDesign? 6.12. Making the Design Look Nice 6.12.1. Can the tool automatically place my instances on the Canvas to make it look nice? 6.12.2. My design has a lot of connections, which make my design hard to read. What do I do? 6.12.3. My instance has too many pins on it; how can I minimize that? 6.12.4. I missed one pin that needs to be part of that group? How do I add a pin after I already have the group? 6.12.5. How do I remove a pin that I don't want inside the group? 6.12.6. How can I improve the readability of my design on the Canvas? 6.13. Generating the Design 6.13.1. Now that I am done connecting my design, how do I finish it so that I can proceed to synthesis? 6.13.2. I get a message that my SmarDesign cannot be generated due to errors. What do I do and what is the Design Rules Check? 6.13.3. What does this error mean and how do I fix it? 7. Appendix B - Glossary 8. Appendix C - DRC Check 8.1. Message Types and Corrective Actions 9. Revision History 10. Microchip FPGA Support The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service