Pinout Diagram

The WLR089U0 module pinout diagram is shown in the following figure.

Figure 1. WLR089U0 Module Pinout Diagram

The following table describes the module pin assignment and descriptions. The ATSAMR34J18B pin numbers are added here for reference. For more details on the SiP pin descriptions, refer to SAM R34/R35 Low Power LoRa Sub-GHz SiP Datasheet (DS70005356).

Table 1. WLR089U0 Module Pinout Assignment

WLR089U0 Module

ATSAMR34J18B SiP

Pin No.

Pin Name

Possible Peripheral Function(1)

SiP Pin No.

Pin Function

1

GND

B5, B7, D4, D6, B3, E2, A2, B2, E1, F2, G2, G3, G5, G6, G7 and H5

Ground

2

3

VCC

A7, A8, G4 and H8 VDDIN, VDDIO2, VDDIO1 and VBAT_DIG, respectively

4

5

PA07

ADC_AIN[7]

F3

EIC_EXTINT[7], RSTC_EXTWAKE[7], ADC_AIN[7], AC_AIN[3], SERCOM0/PAD[3], TCC1/WO[1], CCL0/OUT[0]

6

PA08

GPIO

F4

EIC_NMI, ADC_AIN[16], PTC_X[0], PTC_Y[6], SERCOM0/PAD[0], SERCOM2/PAD[0], TCC0/WO[0], TCC1/WO[2], CCL1/IN[3]

7

PA27

GPIO

E4

EIC_EXTINT[15], GCLK_IO[0]

8

PA16

SERCOM1_I2C_SDA

F7

EIC_EXTINT[0], PTC_X[4], SERCOM1/PAD[0], SERCOM3/PAD[0], TCC2/WO[0], TCC0/WO[6], GCLK_IO[2], CCL0/IN[0]

9

PA17

SERCOM1_I2C_SCL

E6

EIC_EXTINT[1], PTC_X[5], SERCOM1/PAD[1], SERCOM3/PAD[1], TCC2/WO[1], TCC0/WO[1], GCLK_IO[3], CCL0/IN[1]

10

PA18

PWM_T0_W2

E7

EIC_EXTINT[2], PTC_X[6], SERCOM1/PAD[2], SERCOM3/PAD[2], TC4/WO[0], TCC0/WO[2], AC/CMP[0], CCL0/ IN[2]

11

PA19

PWM_T0_W3

E8

EIC_EXTINT[3], PTC_X[7], SERCOM1/PAD[3], SERCOM3/PAD[3], TC4/WO[1], TCC0/WO[3], AC/CMP[1], CCL0/OUT[0]

12

GND

B5, B7, D4, D6, B3, E2, A2, B2, E1, F2, G2, G3, G5, G6, G7 and H5

Ground

13

PA15

GPIO

G8

EIC_EXTINT[15], SERCOM2/PAD[3], TC4/WO[1], TCC0/WO[5], GCLK_IO[1]

14

PA14

GPIO

F8

EIC_EXTINT[14], SERCOM2/PAD[2], TC4/WO[0], TCC0/WO[4], GCLK_IO[0]

15

GND

B5, B7, D4, D6, B3, E2, A2, B2, E1, F2, G2, G3, G5, G6, G7 and H5

Ground

16

PB22

SERCOM5_SPI_MOSI

E5

EIC_EXTINT[6], SERCOM5/PAD[2], TC3/WO[0], GCLK_IO[0], CCL0/IN[0]

17

PA23

SERCOM5_SPI_Slave_Select

D7

EIC_EXTINT[7], PTC_X[11], SERCOM3/PAD[1], SERCOM5/PAD[1], TC0/WO[1], TCC0/WO[5], USB/SOF 1kHz[6], GCLK_IO[7], CCL2/IN[1]

18

PB23

SERCOM5_SPI_CLK

C7

EIC_EXTINT[7], SERCOM5/PAD[3], TC3/WO[1], GCLK_IO[1], CCL0/OUT[0]

19

PB02

SERCOM5_SPI_MISO

B4

EIC_EXTINT[2], ADC_AIN[10], SERCOM5/PAD[0], TC2/WO[0], SUPC/OUT[1], CCL0/OUT[0]

20

PA22

GPIO

D8

EIC_EXTINT[6], PTC_X[10], SERCOM3/PAD[0], SERCOM5/PAD[0], TC0/WO[0], TCC0/WO[4], GCLK_IO[6], CCL2/IN[0]

21

PA25

USB_DP[6]

C8

EIC_EXTINT[13], SERCOM3/PAD[3], SERCOM5/PAD[3], TC1/WO[1], TCC1/WO[3], USB/DP[6], CCL2/OUT[2]

22

PA24

USB_DM[6]

B8

EIC_EXTINT[12], SERCOM3/PAD[2], SERCOM5/PAD[2], TC1/WO[0], TCC1/WO[2], USB/DM[6], CCL2/IN[2]

23

GND

B5, B7, D4, D6, B3, E2, A2, B2, E1, F2, G2, G3, G5, G6, G7 and H5

Ground

24

GND

Ground

25

RESET

RESET_N

B6

RESET

26

VSW

VSW

A6

VSW

27

VDDCORE

VDDCORE

A5

VDDCORE

28

PA28

GPIO

C6

EIC_EXTINT[8], GCLK_IO[0]

29

PA31

SWDIO(2)

D5

EIC_EXTINT[11], SERCOM1/PAD[3], TCC1/WO[1], SWDIO(2), CCL1/OUT[1]

30

PA30

SWDCLK(2)

C5

EIC_EXTINT[10], SERCOM1/PAD[2], TCC1/WO[0], SWCLK(2), GCLK_IO[0], CCL1/IN[0]

31

PA05

SERCOM0_UART_RX

C4

EIC_EXTINT[5], RSTC_EXTWAKE[5], ADC_AIN[5], AC_AIN[1], SERCOM0/PAD[1], TCC0/WO[1], CCL0/IN[1]

32

PA04

SERCOM0_UART_TX

D3

EIC_EXTINT[4], RSTC_EXTWAKE[4], VREFB, ADC_AIN[4], AC_AIN[0], SERCOM0/PAD[0], TCC0/WO[0], CCL0/IN[0]

33

PB03

SUPC_VBAT

C3

EIC_EXTINT[3], ADC_AIN[11], SERCOM5/PAD[1], TC2/WO[1], SUPC/VBAT

34

PA06

PTC_Y4

E3

EIC_EXTINT[6], RSTC_EXTWAKE[6], ADC_AIN[6], AC_AIN[2], PTC_Y[4], SERCOM0/PAD[2], TCC1/WO[0], CCL0/IN[2]

35

GND

B5, B7, D4, D6, B3, E2, A2, B2, E1, F2, G2, G3, G5, G6, G7 and H5

Ground

36

GND

Ground

37

GND

Ground

38

GND

Ground

39

GND

Ground

40

GND

Ground

41

TPAD_GND

Thermal Pad Ground

Notes:
  1. 1.The peripheral function indicated in this column is based on the reference design. This is one of the possibilities as each WLR089U0 pin supports several multiplexed peripheral functions mentioned in the pin function column.
  2. 2.This function is only activated in the presence of a debugger.