Supply Voltage

Table 1.
PIC18LF27/47K40 only
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Characteristic	Min.	Typ.†	Max.	Units	Conditions
Supply Voltage
D002	V_DD		1.8	—	3.6	V	FOSC ≤ 16 MHz
			2.5	—	3.6	V	FOSC > 16 MHz
			3.0	—	3.6	V	FOSC > 32 MHz
RAM Data Retention⁽¹⁾
D003	V_DR		1.5	—	—	V	Device in `SLEEP` mode
Power-on Reset Release Voltage⁽²⁾
D004	V_POR		—	1.6	—	V	BOR or LPBOR disabled⁽³⁾
Power-on Reset Rearm Voltage⁽²⁾
D005	V_PORR		—	0.8	—	V	BOR or LPBOR disabled⁽³⁾
V_DD Rise Rate to ensure internal Power-on Reset signal⁽²⁾
D006	S_VDD		0.05	—	—	V/ms	BOR or LPBOR disabled⁽³⁾
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1.This is the limit to which V_DD can be lowered in Sleep mode without losing RAM data. 2.See the following figure, POR and POR REARM with Slow Rising V_DD. 3.Please see Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications for BOR and LPBOR trip point information.
PIC18F27/47K40 only
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Characteristic	Min.	Typ.†	Max.	Units	Conditions
Supply Voltage
D002A	V_DD		2.3	—	5.5	V	FOSC ≤ 16 MHz
			2.5	—	5.5	V	FOSC > 16 MHz
			3.0	—	5.5	V	FOSC > 32 MHz
RAM Data Retention⁽¹⁾
D003A	V_DR		1.7	—	—	V	Device in `SLEEP` mode
Power-on Reset Release Voltage⁽²⁾
D004A	V_POR		—	1.6	—	V	BOR or LPBOR disabled⁽³⁾
Power-on Reset Rearm Voltage⁽²⁾
D005A	V_PORR		—	1.5	—	V	BOR or LPBOR disabled⁽³⁾
V_DD Rise Rate to ensure internal Power-on Reset signal⁽²⁾
D006A	S_VDD		0.05	—	—	V/ms	BOR or LPBOR disabled⁽³⁾
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1.This is the limit to which V_DD can be lowered in Sleep mode without losing RAM data. 2.See the following figure, POR and POR REARM with Slow Rising V_DD. 3.Please see Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications for BOR and LPBOR trip point information.

Figure 1. POR and POR Rearm with Slow Rising V_DD

Note:

1.When NPOR is low, the device is held in Reset.
2.T_POR 1 μs typical.
3.T_VLOW 2.7 μs typical.