NVMCON1
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NVMREG[1:0] | FREE | WRERR | WREN | WR | RD | ||
AccessR/W | R/W | R/S/HC | R/W/HS | R/W | R/S/HC | R/S/HC | |
Reset0 | 0 | 0 | 0 | 0 | 0 |
NVM Region Selection bits
Value | Description |
---|---|
10 | PFM locations write access |
x1 | User IDs, Configuration Bits, Rev ID and Device ID locations write access |
00 | Data EEPROM Memory locations write access |
Value | Description |
---|---|
1 | Performs an erase operation on the next WR command |
0 | The next WR command performs a write operation |
Value | Description |
---|---|
1 | A write
operation was interrupted by a Reset (hardware set),
or the WR bit was set during
one of the following conditions:
|
0 | All write operations have completed normally |
Program/Erase Enable bit
Value | Description |
---|---|
1 | Allows program/erase and refresh cycles |
0 | Inhibits programming/erasing and user refresh of NVM |
Value | Name | Description |
---|---|---|
1 | NVMREG=00 | Initiates an erase/program cycle at the corresponding Data EEPROM Memory location specified by NVMADR |
1 | NVMREG=10 and TBLPTR21=0 | Initiates the PFM write operation with data from the holding registers |
1 | NVMREG=x1 and TBLPTR21 =1 | Initiates the User ID write operation with data from the holding registers or single Config byte at TBLPTR |
0 | NVMREG=xx | NVM program/erase operation is complete and inactive |
Value | Description |
---|---|
1 | Initiates a read at address pointed by NVMREG and NVMADR, and loads data into NVMDAT |
0 | NVM read operation is complete and inactive |