SSPxCON2

MSSP Control Register 2
Note:
  1. 1.The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
  2. 2.If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
Name:
SSPxCON2
Offset:
0xF97,0xE97
Reset:
Access:
Bit76543210
GCENACKSTATACKDTACKENRCENPENRSENSEN
AccessR/WR/W/HCR/WR/WR/WR/WR/WR/W
Reset00000000

Bit 7 – GCEN

General Call Enable bit (Slave mode only)
ValueNameDescription
x Master mode Don't care
1 Slave mode General call is enabled
0 Slave mode General call is not enabled

Bit 6 – ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

Acknowledge Status bit (Master Transmit mode only)

ValueDescription
1 Acknowledge was not received from slave
0 Acknowledge was received from slave

Bit 5 – ACKDT

Acknowledge Data bit (Master Receive mode only)(1)
ValueDescription
1 Not Acknowledge
0 Acknowledge

Bit 4 – ACKEN

Acknowledge Sequence Enable bit(2)
ValueDescription
1 Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; 
automatically cleared by hardware
0 Acknowledge sequence is Idle

Bit 3 – RCEN

Receive Enable bit (Master Receive mode only)(2)
ValueDescription
1

Enables Receive mode for I2C

0

Receive is Idle

Bit 2 – PEN

Stop Condition Enable bit (Master mode only)(2)
ValueDescription
1 Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 Stop condition is Idle

Bit 1 – RSEN

Repeated Start Condition Enable bit (Master mode only)(2)
ValueDescription
1 Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 Repeated Start condition is Idle

Bit 0 – SEN

Start Condition Enable bit (Master mode only)(2)
ValueDescription
1 Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 Start condition is Idle