Timer1 Gate Source Selection

The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by the GPOL bit. The table below lists the gate source selections.

Table 1. Timer Gate Signal Selection
GSS Gate Source
Timer1 Timer3 Timer5
1111 Reserved Reserved Reserved
1110 ZCDOUT ZCDOUT ZCDOUT
1101 CMP2OUT CMP2OUT CMP2OUT
1100 CMP1OUT CMP1OUT CMP1OUT
1011 PWM4OUT PWM4OUT PWM4OUT
1010 PWM3OUT PWM3OUT PWM3OUT
1001 CCP2OUT CCP2OUT CCP2OUT
1000 CCP1OUT CCP1OUT CCP1OUT
0111 TMR6OUT (post-scaled) TMR6OUT (post-scaled) TMR6OUT (post-scaled)
0110 TMR5 overflow TMR5 overflow Reserved
0101 TMR4OUT (post-scaled) TMR4OUT (post-scaled) TMR4OUT (post-scaled)
0100 TMR3 overflow Reserved TMR3 overflow
0011 TMR2OUT (post-scaled) TMR2OUT (post-scaled) TMR2OUT (post-scaled)
0010 Reserved TMR1 overflow TMR1 overflow
0001 TMR0 overflow TMR0 overflow TMR0 overflow
0000 Pin selected by T1GPPS Pin selected by T3GPPS Pin selected by T5GPPS

Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1 clock or left asynchronous. For more information refer to the Comparator Output Synchronization section.