(NVM) Nonvolatile Memory Control

Nonvolatile Memory (NVM) is separated into two types: Program Flash Memory (PFM) and Data EEPROM Memory.

PFM, Data EEPROM, User IDs and Configuration bits can all be selected for write access with the NVMREG bits. The NVMREG bits are don't cares for read access.

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device.

NVM can be protected in two ways, by either code protection or write protection. Code protection (CP and CPD bits in the Configuration Words) disables access, reading and writing to both PFM and Data EEPROM Memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all nonvolatile memory, Configuration bits and User IDs.

Write protection prohibits self-write and erase to a portion or all of the PFM, as defined by the WRT bits in the Configuration Words. Write protection does not affect a device programmer’s ability to read, write or erase the device.

Table 1. NVM Organization and Access Information

ICSP™ Addr<21:0>

Execution User Access
User Flash Memory
(PFM) 00 0000h
 • • •
01 FFFFh Read 10 Read/
Write(1) (3)
User IDs(2) 20 0000h
• • •
20 000Fh No Access x1 Read/
Write (3)
Reserved 20 0010h No Access (3)
Configuration 30 0000h
• • •
30 0000Bh No Access x1 Read/
Write(1) (3)
Reserved 30 000Ch No Access (3)
30 FFFFh
User Data Memory
(Data EEPROM) 31 0000h
• • •
31 0YYYh(4) No Access 00 (3) Read/


Reserved 32 0000h No Access (3)
Revision ID/

Device ID

• • •
3F FFFFh No Access x1 Read (3)
  1. 1.Subject to Memory Write Protection settings.
  2. 2.User IDs are eight words. There is no code protection, table read protection or write protection implemented for this region.
  3. 3.Reads as ‘0’. Writes set the WRERR bit and clear the WR bit.
  4. 4.Address range shown is for ICSP only. User mode read and write must use NVMADR with upper limit of 0YYYh to specify the address. YYY is the hexidecimal equivalent of one less than the number of bytes in the EEPROM data memory.