# Internal Clock Source

When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input.

Important: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions:
• Timer1 enabled after POR
• Write to TMRxH or TMRxL
• Timer1 is disabled
• Timer1 is disabled (TMRxON = 0) when TxCKI is high then Timer1 is enabled (TMRxON = 1) when TxCKI is low. Refer to the figure below.
Figure 1. Timer1 Incrementing Edge
Note:
1. 1.Arrows indicate counter increments.
2. 2.In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.