ADCON0
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADON | ADCONT | ADCS | ADFM | ADGO | |||
AccessR/W | R/W | R/W | R/W | R/W/HC | |||
Reset0 | 0 | 0 | 0 | 0 |
ADC Enable bit
Value | Description |
---|---|
1 | ADC is enabled |
0 | ADC is disabled |
ADC Continuous Operation Enable bit
Value | Description |
---|---|
1 | ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is set) or until ADGO is cleared (regardless of the value of ADSOI) |
0 | ADC is cleared upon completion of each conversion trigger |
ADC Clock Selection bit
Value | Description |
---|---|
1 | Clock supplied from FRC dedicated oscillator |
0 | Clock supplied by Fosc, divided according to ADCLK register |
ADC results Format/alignment Selection
Value | Description |
---|---|
1 | ADRES and ADPREV data are right-justified |
0 | ADRES and ADPREV data are left-justified, zero-filled |
ADC Conversion Status bit
Value | Description |
---|---|
1 | ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the ADCONT bit |
0 | ADC conversion completed/not in progress |