NVM Unlock Sequence

The unlock sequence is a mechanism that protects the NVM from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations:

The unlock sequence consists of the following steps and must be completed in order:

Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume with the next instruction.

Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed.

Figure 1. NVM Unlock Sequence Flowchart

NVM Unlock Sequence

   BCF     INTCON,GIE      ; Recommended so sequence is not interrupted
   BANKSEL NVMCON1         ; Bank to NVMCON1 register
   BSF     NVMCON1,WREN    ; Enable write/erase
   MOVLW   55h             ; Load 55h
   MOVWF   NVMCON2         ; Step 1: Load 55h into NVMCON2
   MOVLW   AAh             ; Step 2: Load W with AAh
   MOVWF   NVMCON2         ; Step 3: Load AAh into NVMCON2
   BSF     NVMCON1,WR      ; Step 4: Set WR bit to begin write/erase
   BSF     INTCON,GIE      ; Re-enable interrupts
  1. 1.Sequence begins when NVMCON2 is written; following 4 steps must occur in the cycle-accurate order shown. If the timing of the four steps is corrupted by an interrupt or a debugger Halt, the action will not take place.
  2. 2.Opcodes shown are illustrative; any instruction that has the indicated effect may be used.