Sleep Mode

Sleep mode is entered by executing the SLEEP instruction, while the Idle Enable (IDLEN) bit of the CPUDOZE register is clear (IDLEN = 0).

Upon entering Sleep mode, the following conditions exist:

  1. 1.WDT will be cleared but keeps running if enabled for operation during Sleep
  2. 2.The PD bit of the STATUS register is cleared
  3. 3.The TO bit of the STATUS register is set
  4. 4.The CPU clock is disabled
  5. 5.LFINTOSC, SOSC, HFINTOSC and ADCRC are unaffected and peripherals using them may continue operation in Sleep.
  6. 6.I/O ports maintain the status they had before Sleep was executed (driving high, low, or high-impedance)
  7. 7.Resets other than WDT are not affected by Sleep mode

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules.