Correction by AC Coupling

When the external voltage source is sinusoidal, the effects of the ZCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a capacitor, in addition to the voltage reducing resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual zero crossing event. The phase shift will be the same for both rising and falling zero crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift is negligible.

To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to obtain a peak current of 300 μA. Next, arbitrarily select a suitably large non-polar capacitor and compute its reactance, Xc, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage, and phase shift by the formulas shown below.

When this technique is used and the input signal is not present, the ZCD will tend to oscillate. To avoid this oscillation, connect the ZCD pin to VDD or GND with a high-impedance resistor such as 200K.

Figure 1. R-C Equations

VPEAK = external voltage source peak voltage

f = external voltage source frequency

C = series capacitor

R = series resistor

VC = Peak capacitor voltage

TΦ = Time ZC event occurs before actual zero crossing

Z=VPEAK3×104

XC=12πfC

R=Z2XC2

VC=XC(3×104)

Φ=tan-1θ(XCR)

TΦ=Φ2πf

Figure 2. R-C Calcuation Example

Vrms=120

VPEAK=Vrms×2=169.7

f=60Hz

C=0.1μF

Z=VPEAK3×104=169.73×104=565.7kΩ

XC=12πfC=12π×60×107=26.53kΩ

R=Z2XC2=565.1kΩ(computed)

Ra=560kΩ(used)

ZR=Ra2+XC2=560.6kΩ

IPEAK=VPEAKZR=302.7×106A

VC=XC×IPEAK=8.0V