The following table shows how some of the other features of CCP modes can be applied using UTMR:
| Feature (Capture/Compare modes) | CCP | UTMR |
|---|---|---|
| Capture Sources | The capture source can be selected using CTS bits. | The ERS input is used as a capture trigger and can be selected using TUxyERS register. |
| Timer Mode | TMR1 must be running in Timer mode or Synchronized counter mode. The Capture/Compare may not work in Asynchronous Counter mode. | UTMR can operate in any mode for Capture/Compare operation to happen. |
| Prescaler | Outside of the prescalers associated with the different time bases, the CCPx input has 4 prescaler settings available for Capture operation. | UTMR has 256 programmable clock prescaler options ranging from 1:1 to 1:256, which can be selected using TUxyPS register. CLC and/or NCO can be used to prescale the ERS input. |
| Output | CCP output can be set, cleared, toggled, or pulsed based on the mode of operation. | Use OM = Pulse mode to pulse the output for one single timer clock period upon each PR match. |
| Interrupts | CCPxIF interrupt is triggered when either a capture event occurs, or a compare match occurs. | CIF capture interrupt represents a captured event. PRIF period interrupt represents a compare match event. |
| Sleep Mode Operation | CCP module operates as long as the underlying time base is active. | UTMR continues to operate as long as the clock is active, and wakes up the CPU if interrupts are enabled. |
| Feature (PWM mode) | CCP | UTMR |
|---|---|---|
| Timer Mode | TMR2 must be running at FOSC/4 clock for correct operation. | UTMR requires a periodic ERS input of the desired PWM period as the time base. The UTMR rollover period must be greater than or equal to the ERS input period for correct operation. |
| PWM Period | The PWM period is specified by the T2PR register of TMR2 resource. | The PWM period is the period of the ERS input signal. |
| PWM Duty Cycle | The PWM duty cycle is determined by the 10-bit value in the CCPRx register. FMT bit controls the alignment of the 10-bit data in the CCPRx register. The CCPRx register double buffers the PWM duty cycle to avoid glitches when changing the duty cycle. | The PWM duty cycle is determined by the PR value in the TUxyPR period register. The TUxyPR period register is also double-buffered to avoid glitches when changing the duty cycle. |
| PWM Resolution | The maximum PWM resolution is 10 bits when T2PR = 0xFF. | The maximum PWM resolution is the size of the UTMR when the UTMR rollover period matches the ERS input period. |
| PWM Output | The CCPx output is a left-aligned PWM signal. | Use OM = Level mode to generate a PWM output. Set OPOL =
0 to generate a left-aligned PWM signal and OPOL =
1 to generate a right-aligned PWM signal. Note: The PR value might
differ based on left-aligned or right-aligned PWM
signal.
|
| Sleep Mode Operation | PWM is not functional in Sleep mode because TMR2 is derived from FOSC. | UTMR continues to operate in Sleep mode as long as the periodic ERS input is available and the UTMR clocks are active. |
The period of the PWM is dependent on the period of the ERS input signal:
When OPOL = 0 (left-aligned PWM), the PR value determines the ON time. Hence, the pulse width of the signal is:
When OPOL = 1 (right-aligned PWM), the PR value determines the OFF time. Hence, the pulse width of the signal is:
The resolution of the PWM is a function of the PWM period, UTMR rollover period, and UTMR size. The maximum PWM resolution is the size of the UTMR, when the UTMR rollover period matches the PWM period.