The following table shows how some of the other features of SMT can be applied using UTMR:
| Feature | SMT | UTMR |
|---|---|---|
| Active Clock Edge | SMT increments at every rising edge of clock by default. The CPOL bit can use used to change the active clock edge. | Use CPOL bit to select the active clock edge. By default, CPOL = Falling Clock Edge. |
| Synchronization | SMT operates asynchronous to the system clock. All input and output signals are synchronized to the SMT clock. | UTMR also operates asynchronous to the system clock. Set CSYNC = Sync to synchronize signals and commands going in and out of the UTMR module. |
| Prescaler | TMR2 has 4 programmable input prescaler options ranging from 1:1 to 1:8, which can be selected using PS bits. | UTMR has 256 programmable clock prescaler options ranging from 1:1 to 1:256, which can be selected using TUxyPS register. |
| Input Source and Polarity | SMT signal and window sources are selected using SSEL and WSEL bits. The polarity is selected using SPOL and WPOL bits. | UTMR has only one ERS input selectable using TUxyERS register and polarity controlled using EPOL bit. Refer to Table 5-1 UTMR Settings for Different STM Modes for details on how the SMT signal and window inputs are mapped to ERS and/or UTMR clock. |
| Buffered Read/Write | The 24-bit SMTxTMR timer/counter register is not guarded for atomic
access and should not be accessed when GO = 1. |
The TUxyTMR timer/counter register is not guarded for atomic access. However, the TUxyPR period register is double-buffered. Refer to section 1.1 UTMR Size and Buffered Access for details on UTMR buffered access to registers. |
| Manual Reset | Setting RST bit clears the timer atomically. | Setting CLR command bit clears the timer atomically. |
| Limit Mode | The counter can be prevented from resetting at the end of the timer
period by using the STP bit. When STP = 1, the SMTxTMR
will stop and remain equal to the SMTxPR register. When STP =
0, the SMTxTMR register resets at the end of the
period. |
Set RESET = None and LIMIT = Enabled to prevent the TUxyTMR counter from advancing beyond PR. Even though the counter does not advance, the timer is still “running” (RUN status bit and Level Output remain asserted) unless a Stop event occurs. |
| Capture Registers | The SMTxCPW and SMTxCPR capture registers capture the value of the SMTxTMR register based on the SMT mode of operation. These registers can also be updated with the current SMTxTMR value by setting the CPWUP and CPRUP bits respectively. | UTMR has only one TUxyCR capture register. Refer to Table 5-1 UTMR Settings for Different STM Modes for details on how this capture register can be used in different modes. The TUxyCR capture register can be updated with the current value of the TUxyTMR counter register by setting the CAPT command bit. |
| Status Information |
Timer run status is indicated by TS bit. Signal status is indicated by AS bit. Window status is indicated by WS bit. All status bits are subject to synchronization delays. |
Timer run status is indicated by RUN bit. CLC can be configured as a latch to indicate signal and window status. |
| Acquisition Mode | When REPEAT = 0, SMT operates in single acquisition
mode, timer stops incrementing and GO bit is cleared after each
acquisition. Set REPEAT = 1 to operate
continuously. |
Enable One-Shot mode (OSEN = Enabled) to operate in single acquisition mode, the timer stops and ON bit is cleared. Disable One-Shot mode to operate continuously. |
| Output | SMT output pulses every period match for one instruction clock. | Use OM = Pulse mode to pulse the output for one single timer clock period upon each PR match. |
| Interrupts |
SMTxPWAIF pulse-width acquisition interrupt triggers when SMTxCPW register is updated with SMTxTMR register value.
SMTxPRAIF period acquisition interrupt triggers when SMTxCPR register is updated with SMTxTMR register value.
SMTxIF period match interrupt occurs when SMTxTMR register equals SMTxPR register. |
SMTxPWAIF and SMTxPRAIF interrupts are represented as CIF capture interrupt in UTMR, which is triggered any time a capture event happens.
SMTxIF interrupt can be represented as PRIF period interrupt in UTMR, which is triggered at every PR match. |
| Sleep Mode Operation | SMT continues to operate as long as the clock is active, and wakes up the CPU if interrupts are enabled. | UTMR continues to operate as long as the clock is active, and wakes up the CPU if interrupts are enabled. |