In the Free-Running Period mode of TMR2, the value of the T2TMR timer register is compared to the T2PR period register on each clock cycle. Upon a period match, the T2TMR timer register is reset in the next clock cycle, and continues counting. The UTMR operates in a similar way: the TUxyTMR timer/counter register is compared to the TUxyPR period register on each timer clock cycle. The RESET bits can be set to reset the counter upon a period register match (PR match). The following table shows UTMR settings in different TMR2 Free-Running Period modes:
| TMR2 MODE[4:0] | TMR2 Mode | UTMR Settings | Comments | |||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Output | Operation | Start | Reset | Stop | START | RESET | STOP | Other | ||
00000 |
Period Pulse | Software gate | ON = 1 |
— | ON = 0 |
None (ON = 1) |
At PR Match | None | — | — |
00001 |
Hardware gate, active-high | ON = 1 (and) ERS = 1 |
— | ON = 0 (or) ERS = 0 |
ERS Level - 1 | Either ERS Edge | — | — | ||
00010 |
Hardware gate, active-low | ON = 1 (and) ERS = 0 |
— | ON = 0 (or) ERS = 1 |
EPOL = Inverted | — | ||||
00011 |
Period Pulse with Hardware Reset | Rising or falling edge Reset | ON = 1 |
Either ERS Edge | ON = 0 |
Either ERS Edge | At Start + PR Match | None | — | UTMR requires an edge to start for the very first time. |
00100 |
Rising edge Reset | Rising ERS Edge | Rising ERS Edge | — | ||||||
00101 |
Falling edge Reset | Falling ERS Edge | EPOL = Inverted | |||||||
00110 |
Low level Reset | ERS = 0 |
ON = 0 (or) ERS = 0 |
None (ON = 1) |
ERS Level - 0 + PR Match | None | — | — | ||
00111 |
High level Reset | ERS = 1 |
ON = 0 (or) ERS = 1 |
EPOL = Inverted | — | |||||