Using UTMR as Timer 1 (TMR1) with Gate Control

TMR1 is a 16-bit timer which adds gate control features to the timer functionality. To implement the same gate control features in UTMR, the ERS signal acts as the gate. The Start and Stop conditions are tied to specific ERS events which signify the gate start and completion events, respectively. At every gate completion event (Stop condition), the current timer value is captured into the TUxyCR capture register and CIF capture interrupt occurs. The following table shows UTMR settings in different TMR1 modes:

Table 1. UTMR Settings for Different TMR1 Modes
TMR1 Mode UTMR Settings Comments
START RESET STOP Other
GE - Gate Enable Rising ERS Edge None Either ERS Edge — —
GPOL - Gate Polarity Rising ERS Edge None Either ERS Edge EPOL = Inverted —
GTM - Gate Toggle Mode Rising ERS Edge None Rising ERS Edge — The CLC or NCO is used as a 1:2 frequency divider, which feeds into UTMR as ERS source.
GSPM - Gate Single Pulse Mode Rising ERS Edge None Either ERS Edge OSEN = Enabled —
GSPM + GTM Rising ERS Edge None Rising ERS Edge OSEN = Enabled —