Other TMR2 Features

The following table shows how some of the other features of TMR2 can be applied using UTMR:

Table 1. Features Comparison between TMR2 and UTMR
Feature	TMR2	UTMR
Active Clock Edge	TMR2 increments at every rising edge of clock by default. The CPOL bit can use used to change the active clock edge.	Use CPOL bit to select the active clock edge. By default, CPOL = Falling Clock Edge.
Synchronization	The prescaler output can be synchronized to Fosc/4 by setting the PSYNC bit. The ON bit can be synchronized to Fosc/4 by setting the CSYNC bit.	Synchronizing prescaler output is not required for UTMR because the timer is completely asynchronous to the system clock. The CSYNC bit is used to synchronize signals and commands going in and out of the UTMR module.
Prescaler	TMR2 has 8 programmable input prescaler options ranging from 1:1 to 1:128, which can be selected using CKPS bits.	UTMR has 256 programmable clock prescaler options ranging from 1:1 to 1:256, which can be selected using TUxyPS register.
Postscaler	TMR2 has a programmable postscaler ranging from 1:1 to 1:16, which can be selected using OUTPS bits. The internal postscaler counter is incremented at every period match.	UTMR does not has any postscaler because the module is not supposed to be used as a time base for PWM.
Output	The TMR2 output pulses for a single timer clock period upon each time the internal postscaler counter matches with the OUTPS bits postscaler selection.	Use OM = Pulse mode to pulse the output for one single timer clock period upon each PR match.
Interrupts	The TMR2IF interrupt is generated every time an output pulse is generated, i.e. when the internal postscaler counter matches with the OUTPS bits postscaler selection.	PRIF period interrupt can be used to signify when a PR match happens.
Sleep Mode Operation	TMR2 halts when PSYNC = `1`. When PSYNC = `0`, TMR2 continues operating, as long as the clock is active, and wakes up the CPU if interrupts are enabled.	UTMR continues to operate as long as the clock is active, and wakes up the CPU if interrupts are enabled.