Commonly Used UTMR Settings

As a reference, the following table describes the selections for the most commonly used settings for the UTMR configuration used throughout this document. Refer to the device specific data sheet or TB3264 for more information.

Table 1. Commonly Used UTMR Settings
UTMR Bit Setting	Description	Possible Selections
START	Start condition of the timer	`00` = None (ON = `1`) `01` = Either ERS Edge `10` = Rising ERS Edge `11` = ERS Level - 1
RESET	Reset condition of the timer	`00` = None `01` = ERS Level - 0 + PR Match `10` = at Start + PR Match `11` = at PR Match
STOP	Stop condition of the timer	`00` = None `01` = Either ERS Edge `10` = Rising ERS Edge `11` = at PR Match
CPOL	Clock polarity – selects the active clock edge	`0` = Falling Clock Edge (default) `1` = Rising Clock Edge
EPOL	ERS polarity – inverts the polarity of ERS signals	`0` = True ERS Levels (default) `1` = Inverted ERS Levels
OSEN	One-shot mode enable – stops the timer and then disables it (ON = `0`)	`0` = Disabled (default) `1` = Enabled
LIMIT	Limit mode enable - prevents the counter from exceeding the PR value	`0` = Disabled (default) `1` = Enabled
CAPT	Capture command bit – captures the current counter value in the capture register	`0` = Capture is complete (or not started) `1` = Counter value capture in progress
CLR	Clear command bit – clears the counter and prescaler counter values	`0` = Clearing is complete (or not started) `1` = Counter/Prescaler counter value clear in progress
OM	Output mode – chooses the type of output	`0` = Pulse Output (default) `1` = Level Output
OPOL	Output polarity – chooses the polarity of the output	`0` = Low output when idle (default) `1` = High output when idle
CSYNC	Clock synchronization – synchronizes ERS and other input/output signals and commands to timer clock	`0` = Disabled/Async `1` = Enabled/Sync (default)
TUCHAIN	Chains two UTMR instances to form a bigger timer	Refer to device specific data sheet