The following table shows how some of the other features of TMR0 can be applied using UTMR:
| Feature | TMR0 | UTMR |
|---|---|---|
| Active Clock Edge | TMR0 increments at every rising edge of clock. | Set CPOL = Rising Clock Edge to increment UTMR at rising clock edges. |
| Synchronization | TMR0 can operate either synchronous or asynchronous to instruction clock (Fosc/4) based on ASYNC bit setting. | UTMR always operates asynchronous to the system clock. The CSYNC bit is used to synchronize signals and commands going in and out of the UTMR module. |
| Buffered Read/Write | Buffered read and write is available in 16-bit mode. | The TUxyTMR timer/counter register is not guarded for atomic access. However, the TUxyPR period register is double-buffered. Refer to section 1.1 UTMR Size and Buffered Access for details on UTMR buffered access to registers. |
| Prescaler | TMR0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768, which can be selected using CKPS bits. | UTMR has 256 programmable clock prescaler options ranging from 1:1 to 1:256, which can be selected using TUxyPS register. |
| Postscaler | TMR0 has a programmable postscaler ranging from 1:1 to 1:16, which can be selected using OUTPS bits. | UTMR does not has any postscaler because the module is not supposed to be used as a time base for PWM. |
| Output | TMR0 output toggles on every match between TMR0L and TMR0H in 8-bit mode, or when TMR0H:TMR0L rolls over in 16-bit mode. If the output postscaler is used, the output is scaled by the ratio selected. | Use OM = Pulse output to pulse the output at every PR match for one timer clock period. To pulse the output at timer overflow (for 16-bit TMR0 mode), set TUxyPR to the maximum value. Toggle output feature is not available in UTMR. |
| Interrupt | TMR0IF interrupt occurs every time TMR0 output toggles. | ZIF zero interrupt can be used to identify when the timer resets or rolls-over to zero. Alternatively, PRIF period interrupt can be used to identify a PR match (as in 8-bit TMR0 mode) and a roll-over (as in 16-bit TMR0 mode) when TUxyPR is set to the maximum value. |
| Sleep Mode Operation | TMR0 halts when operating synchronously. In Asynchronous mode, TMR0 continues operating as long as the clock is active, and wakes up the CPU if interrupts are enabled. | UTMR continues to operate as long as the clock is active, and wakes up the CPU if interrupts are enabled. |