Follow these steps to generate the project using MCC:
If the MCC is not installed, please follow the instructions provided on the MPLAB®InstallCode Configurator (MCC) webpage.
After the configurations made above, the TCD0 clock will have a frequency of 125 kHz.
The TCD0 will be configured to generate an event every time the counter reaches the value from CMPBSET register. The time difference between two consecutive events is TCD0 clock/CMPBCLR.
Because the events must occur with a frequency of 40 Hz, results that CMPBCLR = TCD0 clock/40 Hz = 0xC36.
After the configurations made above TCD will generate an event every 25 ms. This event will be later connected on this demo with the LUT0, TCA0 and TCA1.
In decimal 0x22=34, which is the number of dots from a SOS message period. In this way the TCA0 output will have a resolution of 1 dot.
TCA0 will count every time an event from TCD0 occurs.
In decimal 0x22=34, which is the number of dots from a SOS message period. In this way the TCA1 output will have a resolution of 1 dot.
TCA1 will count every time an event from TCD0 occurs.
The Filter from LUT0 is used in SYNC mode with feedback loop in order to obtain the signal which contains the pattern of letter ‘S’. It divides the frequency of events triggered by TCD0 with a factor of 4.
The value of OUT bits is negated because the output of LUT1 will drive the CNANO board LED, which works on invert logic (logic ’0’ - ON, logic ‘1’ - OFF).