Output Enable Timer Protection for GPIO Configuration

When the RESET Pin Configuration (RSTPINCFG) bits in FUSE.SYSCFG0 are 0x0, the RESET pin configured as GPIO. To avoid the potential conflict between the GPIO actively driving the output and a 12V UPDI enable sequence initiation, a timer protection is disabling the output enable for a minimum time of 8.8ms after each System Reset.

It is always recommended to issue a System Reset before entering the 12V programming sequence.