Control B - Normal Mode

Name:
CTRLB
Offset:
0x01
Reset:
0x00
Access:
-
Bit76543210
CMPnEN2CMPnEN1CMPnEN0ALUPDWGMODE[2:0]
AccessR/WR/WR/WR/WR/WR/WR/W
Reset0000000

Bit 3 – ALUPD: Auto Lock Update

Auto Lock Update

The Auto Lock Update feature controls the Lock Update (LUPD) bit in the TCA.CTRLE register. When ALUPD is written to ‘1’, LUPD will be set to ‘1’ until the Buffer Valid (CMPnBV) bits of all enabled compare channels are ‘1’. This condition will clear LUPD.

It will remain cleared until the next UPDATE condition, where the buffer values will be transferred to the CMPn registers and LUPD will be set to ‘1’ again. This makes sure that CMPnBUF register values are not transferred to the CMPn registers until all enabled compare buffers are written.

ValueDescription
0 LUPD in TCA.CTRLE not altered by system.
1 LUPD in TCA.CTRLE set and cleared automatically.

Bits 2:0 – WGMODE[2:0]: Waveform Generation Mode

Waveform Generation Mode

These bits select the waveform generation mode, and control the counting sequence of the counter, TOP value, UPDATE condition, interrupt condition, and type of waveform that is generated.

No waveform generation is performed in the normal mode of operation. For all other modes, the result from the waveform generator will only be directed to the PORT pins if the corresponding CMPnEN bit has been set to enable this. The port pin direction must be set as output.

Table 1. Timer Waveform Generation Mode
WGMODE[2:0] Group Configuration Mode of Operation Top Update OVF
000 NORMAL Normal PER TOP TOP
001 FRQ Frequency CMP0 TOP TOP
010 - Reserved - - -
011 SINGLESLOPE Single-slope PWM PER BOTTOM BOTTOM
100 - Reserved - - -
101 DSTOP Dual-slope PWM PER BOTTOM TOP
110 DSBOTH Dual-slope PWM PER BOTTOM TOP and BOTTOM
111 DSBOTTOM Dual-slope PWM PER BOTTOM BOTTOM
ValueNameDescription
0x0 NORMAL Normal operation mode
0x1 FRQ Frequency mode
0x3 SINGLESLOPE Single-slope PWM mode
0x5 DSTOP Dual-slope PWM mode
0x6 DSBOTH Dual-slope PWM mode
0x7 DSBOTTOM Dual-slope PWM mode
Other - Reserved

Bits 4, 5, 6 – CMPnEN: Compare n Enable

Compare n Enable

In the FRQ or PWM waveform generation mode, these bits will override the PORT output register for the corresponding pin.
ValueDescription
0 PORT output settings for the pin with WOn output respected.
1 PORT output settings for pin with WOn output overridden in FRQ or PWM waveform generation mode.