LUT n Control B

SPI connections to the CCL work only in master SPI mode.

USART connections to the CCL work only in asynchronous/synchronous USART master mode.

Name:
LUTCTRLB
Offset:
0x06 + n*0x04 [n=0..1]
Reset:
0x00
Access:
Enable-Protected
Bit76543210
INSEL1[3:0]INSEL0[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 7:4 – INSEL1[3:0]: LUT n Input 1 Source Selection

LUT n Input 1 Source Selection

These bits select the source for input 1 of LUT n:

ValueNameDescription
0x0 MASK Masked input
0x1 FEEDBACK Feedback input
0x2 LINK Linked other LUT as input source
0x3 EVENT0/EVENT1 Event 0 as input source for LUT0 / Event 1 as input source for LUT1
0x4 EVENT2/EVENT3 Event 2 as input source for LUT0 / Event 3 as input source for LUT1
0x5 IO I/O pin LUTn-IN1 input source
0x6 AC0 AC0 OUT input source
0x7 TCB0 TCB WO input source
0x8 TCA0 TCA WO1 input source
0x9 TCD0 TCD WOB input source
0xA USART0 USART TXD input source
0xB SPI0 SPI MOSI input source
0xC AC1 AC1 OUT input source
0xD TCB1 TCB 1 W0 input source
0xE AC2 AC2 OUT input source

Bits 3:0 – INSEL0[3:0]: LUT n Input 0 Source Selection

LUT n Input 0 Source Selection

These bits select the source for input 0 of LUT n:

ValueNameDescription
0x0 MASK Masked input
0x1 FEEDBACK Feedback input
0x2 LINK Linked other LUT as input source
0x3 EVENT0/EVENT1 Event 0 as input source for LUT0 / Event 1 as input source for LUT1
0x4 EVENT2/EVENT3 Event 2 as input source for LUT0 / Event 3 as input source for LUT1
0x5 IO I/O pin LUTn-IN0 input source
0x6 AC0 AC0 OUT input source
0x7 TCB0 TCB WO input source
0x8 TCA0 TCA WO0 input source
0x9 TCD0 TCD WOA input source
0xA USART0 USART XCK input source
0xB SPI0 SPI SCK input source
0xC AC1 AC1 OUT input source
0xD TCB1 TCB 1 W0 input source
0xE AC2 AC2 OUT input source
Other - Reserved