Control A

Name:
CTRLA
Offset:
0x00 [ID-000004d0]
Reset:
0x00
Access:
-
Bit76543210
DORDMASTERCLK2XPRESC[1:0]ENABLE
AccessR/WR/WR/WR/WR/WR/W
Reset000000

Bit 6 – DORD: Data Order

Data Order

ValueDescription
0 The MSB of the data word is transmitted first.
1 The LSB of the data word is transmitted first.

Bit 5 – MASTER: Master/Slave Select

Master/Slave Select

If SS is configured as input and driven low while this bit is '1', this bit is cleared, and the IF flag in SPI.INTFLAGS is set. The user has to write MASTER=1 again to re-enable SPI Master mode.

This behavior is controlled by the Slave Select Disable bit (SSD) in SPI.CTRLB.

ValueDescription
0 SPI Slave mode selected
1 SPI Master mode selected

Bit 4 – CLK2X: Clock Double

Clock Double

When this bit is written to '1' the SPI speed (SCK frequency, after internal prescaler) is doubled in Master mode.

ValueDescription
0 SPI speed (SCK frequency) is not doubled.
1 SPI speed (SCK frequency) is doubled in Master mode

Bits 2:1 – PRESC[1:0]: Prescaler

Prescaler

This bit field controls the SPI clock rate configured in master mode. These bits have no effect in slave mode. The relationship between SCK and the peripheral clock frequency (fCLK_PER) is shown below.

The output of the SPI prescaler can be doubled by writing the CLK2X bit to '1'.
ValueNameDescription
0x0 DIV4 CLK_PER/4
0x1 DIV16 CLK_PER/16
0x2 DIV64 CLK_PER/64
0x3 DIV128 CLK_PER/128

Bit 0 – ENABLE: SPI Enable

SPI Enable

ValueDescription
0 SPI is disabled.
1 SPI is enabled.