Control C

Name:
CTRLC
Offset:
0x02
Reset:
0x00
Access:
-
Bit76543210
CMPDSELCMPCSELFIFTYAUPDATECMPOVR
AccessR/WR/WR/WR/WR/W
Reset00000

Bit 7 – CMPDSEL: Compare D Output Select

Compare D Output Select

ValueNameDescription
0 PWMA Waveform A
1 PWMB Waveform B

Bit 6 – CMPCSEL: Compare C Output Select

Compare C Output Select

ValueNameDescription
0 PWMA Waveform A
1 PWMB Waveform B

Bit 3 – FIFTY: Fifty Percent Waveform

Fifty Percent Waveform

If the two waveforms have identical characteristics, this bit can be written to '1'. This will cause any values written to register CMPBSET/CLR also to be written to the register CMPASET/CLR.

Bit 1 – AUPDATE: Automatically Update

Automatically Update

If this bit is set a synchronization at the end of the TCD cycle is automatically requested after the Compare B Clear High register (CMPBCLRH) is written.

If the Fifty Percent Waveform is enabled by setting the FIFTY bit in this register, writing the Compare A Clear High register will also request a synchronization at the end of the TCD cycle if the AUPDATE bit is set.

Bit 0 – CMPOVR: Compare Output Value Override

Compare Output Value Override

When this bit is written, default values of the Waveform Outputs A and B are overridden by the values written in the Compare x Value in active state bit fields in the Control D register (CTRLD.CMPnxVAL). See the Control D register description for more details.