Control D


Bits 7:5 – INITDLY[2:0]: Initialization Delay

Initialization Delay

These bits defines the initialization/startup delay before the first sample when enabling the ADC or changing to internal reference voltage. Setting this delay will ensure that the reference, muxes, etc are ready before starting the first conversion. The initialization delay will also take place when waking up from deep sleep to do a measurement.

The delay is expressed as a number of CLK_ADC cycles.

0x0 DLY0 Delay 0 CLK_ADC cycles.
0x1 DLY16 Delay 16 CLK_ADC cycles.
0x2 DLY32 Delay 32 CLK_ADC cycles.
0x3 DLY64 Delay 64 CLK_ADC cycles.
0x4 DLY128 Delay 128 CLK_ADC cycles.
0x5 DLY256 Delay 256 CLK_ADC cycles.
Other - Reserved

Bit 4 – ASDV: Automatic Sampling Delay Variation

Automatic Sampling Delay Variation

Writing this bit to '1' enables automatic sampling delay variation between ADC conversions. The purpose of varying sampling instant is to randomize the sampling instant and thus avoid standing frequency components in frequency spectrum. The value of the SAMPDLY bits is automatically incremented by one after each sample.

When the Automatic Sampling Delay Variation is enabled and the SAMPDLY value reaches 0xF, it wraps around to 0x0.
0 ASVOFF The Automatic Sampling Delay Variation is disabled.
1 ASVON The Automatic Sampling Delay Variation is enabled.

Bits 3:0 – SAMPDLY[3:0]: Sampling Delay Selection

Sampling Delay Selection

These bits define the delay between consecutive ADC samples. The programmable Sampling Delay allows modifying the sampling frequency during hardware accumulation, to suppress periodic noise sources that may otherwise disturb the sampling. The SAMPDLY field can be also modified automatically from sampling cycle to another, by setting the ASDV bit. The delay is expressed as CLK_ADC cycles and is given directly by the bitfield setting. The sampling cap is kept open during the delay.