Parallel programming timing in ATmega328PB has been modified, comparing with ATmega328 variants. For details, see the below table, "Parallel Programming Timing Differences".
| Symbol | Parameter | ATmega328PB | ATmega328 variants | Units | ||
|---|---|---|---|---|---|---|
| Min. | Max. | Min. | Max. | |||
| tWLRH | WR Low to RDY/BSY High | 3.2 | 3.4 | 3.7 | 4.5 | ms |
| tWLRH_CE | WR Low to RDY/BSY High for Chip Erase | 9.8 | 10.5 | 7.5 | 9 | ms |
| tBVDV | BS1 Valid to DATA valid | 0 | 350 | 0 | 250 | ns |
| tOLDV | OE Low to DATA Valid | 0 | 350 | -- | 250 | ns |