Correcting Timing Inaccuracies

Since it is not possible to use interrupt driven detection for the C-clock edges in all devices, a polling method is implemented. The consequence of this implementation is that edge detection can be delayed by up to two CPU cycles. Potentially this can make the calibration fail to reach the desired accuracy of 1%. To compensate for this potential timing error, the limits are tightened by two timer-ticks (two CPU-cycles). All calculations of limits and constants are performed by the preprocessor, which uses 64-bit accuracy in AVRASM2. All values that cannot be represented (floats) are rounded towards a tighter accuracy and will therefore not endanger the goal of ±1% accuracy for the oscillator.